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Semiconductor
SD42C/P1008
4Bit Single Chip Microcontroller
Description
The SD42C1008 is a microcomputer of the 4-bit single chip microcomputer SD42xx series which can match an 8-bit microcomputer in the data processing capability. The SD42C1008 can handle 1-bit, 4-bit, and 8-bit data as well as operates at high speed (minimum instruction execution time : 0.95us) it contains a LCD pannel controller/driver.
Ordering Information
Type NO. SD42C1008 Marking SD42C1008 Package Code QFP-80
Pin Configuration
SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 RESETB P53/kS7 P52/kS6 P51/kS5 8777777777766666 0987654321098765
S E G 1 21 S E G 1 32 S E G 1 43 S E G 1 54 S E G 1 65 S E G 1 76 S E G 1 87 S E G 1 98 S E G 2 09 S E G 2 11 0 S E G 2 21 1 S E G 2 31 2 S E G 2 41 3 S E G 2 51 4 S E G 2 61 5 S E G 2 71 6 S E G 2 81 7 S E G 2 91 8 S E G 3 01 9 S E G 3 12 0 C O M 02 1 C O M 12 2 C O M 22 3 C O M 32 4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P50/kS4 P43/kS3 P42/kS2 P41/kS1 P40/kS0 X0 XI TEST XTO XTI VD D P33 53 32 P P31 P30 P13/BUZ P12/SO P11/SI P10/SCK P03/INT3 P02/INT2 P01/INT1 P00/INT0/TI0 P23
SD42C1008
BIAS VLC0 VLC1 VLC2 P60 P61 P62 P63 VS S P80 P81 P82 P83 P20/CL P21 P22 KSI-W029-000
2222233333333334 5678901234567890
1
SD42C/P1008
Features
Memory mapped I/O Program memory : 8192 x 10bits Data memory : 512 x 4bits Instructions - Various bit manipulation - 8-bit data operation - 7-bit relative branch - 1 byte absolute call Instruction cycle times - Main ( XI = 4.19MHz ) . 15.3 us ( XI/64 = 65.5KHz ) . 1.91 us ( XI/8 = 524.0KHz ) . 0.95 us ( XI/4 = 1.05MHz ) - Sub ( XTI = 32.768KHz ) . 122 us ( XTI/4 = 8.19KHz ) 4 Register Bank General register : 8 x 4-bit respectively Accumulator - Bit Accumulator (CY), 4 bit Accumulator (A), 8 bit Accumulator (XA) Multiple vectored interrupt source - External interrupt : 4 - Internal interrupt : 4 Watch timer - fast mode : 3.91 msec - normal mode : 0.5 sec - buzzer output : 1, 2, 4 KHz 64 I/O Pins - LCD driver output pins : 36 . Segment ouput pins : 20 . Segment CMOS output pins : 12 . Common ounput pins : 4 - CMOS input/output pins : 32 Power saving mode - STOP : Main clock, CPU clock stop - STBY : Only CPU clock stop Main clock operation 8-bit serial communication interface - External / Internal clock selection - Mode : Transmit *Receive Receive only Clock continuous LCD controller/driver - selectable number of segments ; 20/24/28/32 segment (4/8/12 lines can be specified as bit ports) - Display mode selection * Static * 1/2 duty (1/2 bias) * 1/3 duty (1/2 bias) * 1/3 duty (1/3 bias) * 1/4 duty (1/3 bias) Key scan - 4, 6, 8 Pins Selectable : Port 4, 5 - Falling edge operation
APPLICATION
Basic interval timer - 8 kinds of period - Used stabilization wait timer to wake up Stop mode One 8-bit timer / event counter VTR, Camera, Rice Cooker, Telephone Blood Pressure Gauge, CD Player
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SD42C/P1008
BLOCK DIAGRAM
BASIC INTERVAL TIMER
PORT2
P20 - P23
IRQBT
PORT3
TIMER/ EVENT COUNTER
P30 - P33
IRQTC0
SD42 CORE
PORT6
P60 - P63
BUZ/P13
WATCH TIMER
PORT8
IRQWT FLCD
P80 - P83
SI/P11 SO/P12 SCK/P10 IRQS0 CLOCKED SERIAL INTERFACE
VLC0~VLC2
PROGRAM MEMORY (8192 X 10BITS)
DATA MEMORY (512 X 4BITS)
TI0/INT0/P00 INT1/P01 INT2/P02 INT3/P03 KS0/P40 KS7/P53
INTERRUPT CONTROL
LCD CONTROL / DRIVER DISPLAY RAM
COM0~COM3
SEG0~SEG19 SEG20~SEG30 (BP0~BP11) BIAS
Fx / 2n
BIT SEQ. BUFFER(16)
CPU CLOCK STOP/ IDLE CONTROL
CLOCK OUTPUT CONTROL
CLOCK DIVIDER
CLOCK GENERATOR
FLCD
XTO
V DD
XTI
KSI-W029-000
P20/CLO
RESETB
TEST
V SS
XO
XI
3
SD42C/P1008
Program Memory(ROM)
CONTENTS
0000H
Vector Address
Prioty
0000H 0002H 0004H
INTERRUPT SUORCE
RESET IRQBT IRQ0 IRQ1 IRQTC0 IRQ2 IRQ3 IRQS0
Reset Signal Basic Interval Timer External interrupt 0 External interrupt 1 Timer Event Counter 0
VECTOR ADDRESS AREA ZERO-PAGE CALL AREA
001FH 0020H
0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H
0 1 2 3 4 6 8 9
002FH 0060H
External interrupt 2
External interrupt 3 Serial I/O 0
8K Byte
0016H 0018H 001AH 001CH
12 13 15
IRQWT IRQKS -
Watch Timer Key Scan
1FFFH
001EH
reserved
Data Memory(RAM)
DIRECT m $00 PAGE0 (256 Byte) $FF $00 PAGE1 (256 Byte) BANK 0 $FF (1K) $00 PAGE2 (256 Byte) $FF $00 PAGE3 (256 Byte) $FF INDIRECT
@HL @DE @DL
STACK
GENERAL REGISTER RB=0 RB=1 RB=2 RB=4
MP=0
SPS=0
MB=0
MB=0
MP=1
SPS=1
MP=2
SPS=2
I/O MEMORY
MP=3
; Usable
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SD42C/P1008
I/O Address Map
ADDRESS b3 318H 319H 31AH 31BH 31CH 31DH 320H 321H 322H 323H 324H 325H 332H 334H 335H 336H 337H 390H 391H 392H 3A0H Hardware Module Name b2 b1 b0 R/W R/W SP1 SP5 IS1 Z OV SP0 SP4 IS0 T W 320H.3 O R/W R/W R/W O O R/W Addressing Unit 1 bit 4 bit 8bit O O O O O Stack pointer low stack pointer high Stack Page Select Low (SPSL) Stack Page Select High (SPSh) Psw low (PSWL) Psw high (PSWH) Clock source select. counter start (ch0) R readable count value (ch0) 00 REMARKS INITIAL VALUE E F 0 0 0 0 00
Stack pointer low (SPL) Stack pointer high (SPH) SP3 AC CY SP2 -
T/E counter mode register 0 (TMOD0) T/E counter register 0 (TMCNT0) T/E reference register 0 (TMREF0) Basic Timer mode register(BMOD) Basic interval timer count register(BITCNT) Watch timer mode register (WMOD) Lcd display mode register (LCDMD) Lcd control register (LCON) Power control register (PCON)
W
count reference register (ch0)
FF
R/W R
332H.3
clock select, Bit start readable count register
0 00
R/W
336H.3
clock/buzzer select. bit3 readable
00
W
O
duty/bias/clock/seg/bitport select
00
W
O O
display ON/OFF system clock select, idle, stop mode
0 00
R/W R/W W O O
3A2H 3A4H
Operating mode register (SCMOD) Clock output mode register (CLOMD)
main/sub system clock select cpu clock output select, clock out EN/DIS
0 00
3A8H 3A9H 3AAH 3ABH 3B2H 3C2H 3C3H 3C4H
Serial interface mode register0 (SIOM0) Serial interface buffer0 (SBUFF0) Power on flag (PONF) IME IPSR3 IPSR2 IPSR1 IPSR0
W
3A8H.3
O
receive/transmit mode. clock select
00
R/W
serial shift register 0
XX
P/W R/W
3B2H.0 3C2H.3
O O
power on reset flag Interrupt priorty select, IME flag.
0 00
External interrupt mode register0 (IMOD0)
W
O
external interrupt 0 edge detection
00
3C5H
External interrupt mode register1 (IMOD1)
W
O
external interrupt 1 edge detection
00
3C6H
External interrupt mode register2 (IMOD2)
W
O
external interrupt 2 edge detection
00
3C7H
External interrupt mode register3 (IMOD3)
W
O
external interrupt 3 edge detection
00
3D8H 3D9H
IE2
IRQ2
IEBT IEWT
IRQBT IRQWT
R/W R/W
O O
O O
Interrupt EN/IRQ flag Interrupt EN/IRQ flag
0 0
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SD42C/P1008
ADDRESS b3 3DAH 3DBH 3DCH 3DDH 3DEH 3E0H 3E1H 3E2H 3E3H 3E4H 3E5H 3E6H 3E7H 3E8H 3E9H 3F0H 3F1H 3F2H 3F3H 3F4H 3F5H 3F6H 3F8H PW03 PW13 PW23 PW33 PW43 PW53 PW63 PW73 PW83 PW93 PW02 PW12 PW22 PW32 PW42 PW52 PW62 PW72 PW82 PW92 PW01 PW11 PW21 PW31 PW41 PW51 PW61 PW71 PW81 PW91 PW00 PW10 PW20 PW30 PW40 PW50 PW60 PW70 PW80 PW90 R/W R/W R/W R/W R/W R/W R/W R/W O O O O O O O O O O O O O O O O O R0 Port Data Register R1 Port Data Register R2 Port Data Register R3 Port Data Register R4 Port Data Register R5 Port Data Register R6 Port Data Register R8 Port Data Register 0 0 0 0 0 0 0 0 W O port 8, 9 mode register (PMGE) 00 W O port 6, 7 mode register (PMGD) 00 W O port 4, 5 mode register (PMGC) 00 W O port 2, 3 mode register (PMGB) 00 IE1 IRQ1 IEKSF Hardware Module Name b2 IRQKS b1 IES0 IETC0 IE0 IE3 b0 IRQS0 IRQTC0 IRQ0 IRQ3 R/W R/W R/W R/W R/W W R/W Addressing Unit 1 bit O O O O O 4 bit O O O O O O 8bit Interrupt EN/IRQ flag Interrupt EN/IRQ flag Interrupt EN/IRQ flag Interrupt EN/IRQ flag Interrupt EN/IRQ flag port 0, 1 mode register (PMGA) REMARKS INITIAL VALUE 0 0 0 0 0 00
PORT0 (R0) PORT1 (R1) PORT2 (R2) PORT3 (R3) PORT4 (R4) PORT5 (R5) PORT6 (R6) PORT8 (R8)
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SD42C/P1008
Pin Description
PIN SYMBOL P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P40 P41 P42 P43 P50 P51 P52 P53 P60 P61 P62 P63 P80 P81 P82 P83 I/O - 4Bit I/O Pin INPUT BP I/O - 4Bit I/O Pin INPUT
BP-PDND
SHARED PIN INT0/TI0 INT1 INT2 INT3 SCK SI SO BUZ
I/O I/O
FUNCTION - Detection edge selectable - With noise elimination function - Edge detection vectored interrupt
RESET INPUT
PORT TYPE BPS
I/O
input pin (detection edge selectable) - Event pulse input port for timer event counter - Serial clock I/O pin
INPUT
BPS
I/O
- Serial data input pin - Serial data output pin - Buzzer output pin
INPUT
BPS
I/O
- 4Bit I/O Port
INPUT
BP
I/O
- 4Bit I/O Port
INPUT
BP
KS0 KS1 KS2 KS3 KS4 KS5 KS6 KS7 I/O - Falling edge detection keyscan input pin INPUT BD I/O - Falling edge detection keyscan input pin INPUT BD
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SD42C/P1008
Pin Description
PIN SYMBOL SEG0 ~ SEG19 SEG20 ~ SEG31 COM0 COM1 COM2 COM3 VLC0 VLC1 VLC2 BIAS XI XO XTI XTO RESETB TEST I O I O I I - LCD power supply bias control - Main system clock input - Main system clock output - Sub system clock input - Sub system clock output - System reset input pin - Chip function test input pin MASK ROM Version OTP ROM Version
IP1 IP2 OSC2 VLC OSC1
SHARED PIN
I/O O
FUNCTION - Segment signal output pin - 1 Bit output port (Bit Port) shared with a segment signal output pin
RESET
PORT TYPE
OP-SEGB
BP0 ~ 11
O
OP-SEGA
O
- Common signal output
OP-COMA
- LCD drive power pin split register network (Mask Option)
VLC
BP
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SD42C/P1008
I/O Circuits
BP
VDD VDD
BPS
VDD VDD
OUTPUT ENABLE
PUR (M.O) PAD
OUTPUT ENABLE
PUR (M.O)
DATA
DATA
PAD
VSS INTERNAL INTERNAL
VSS
BD
VDD
BP-PDND
VDD Output TR Disable (P-CH) PUR (M.O) PAD OUTPUT ENABLE DATA PUR (M.O)
PAD
DATA OUTPUT ENABLE
Output TR Disable (N-CH) VSS
VSS INTERNAL
INTERNAL
OP-COMA
VLC0
OP-SEGA
VLC0
VLC1
VLC1
COM DATA
PAD SEG DATA PAD
VLC2
VLC2
NOTE) PUR : Pull-Up Resistor M.O : Mask Option
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SD42C/P1008
OP-SEGB
VDD
IP1
VDD
VLC0 VLC1 SEG DATA PBIT.X DATA
PAD
PAD VLC2
VSS
IP2
VLC
VDD
PAD
BIAS 2R VLC0 R R=90K R VLC2 VSS R VLC1
VSS
OSC1
OSC2
XI
XO
XTI
XTO
VSS
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SD42C/P1008
Absolute Maximum Ratings
(TA = 0E to 70E, VDD = 5V 10%, fx = 4.19MHz)
PARAMETER Supply Voltage Input Voltage Output Voltage Output Current High SYMBOL VDD VI VO IOH CONDITION All I/O ports One I/O port active All I/O ports active Output Current Low One I/O port active Total value for ports IOL P1, P2, P3, P8 Total value for ports P0, P4, P5, P6 Operating Temperature Storage Temperature TA Tstg RMS Value Peak Value RMS Value -40 to +85 -55 to +125 +60 +100 +60 E E RATING -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -15 -30 Peak Value RMS Value Peak Value +30 +15 +100 mA UNIT V V V mA
* RMS values are calculated as peak value x Duty * Exceeding beyond those listed values under "Absolute Maximum Ratings" may cause permanent
damage to the device.
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SD42C/P1008
DC Electrical Characteristics
(VSS = 0, VDD = 5V 10%, TA = 25E, fX = 4.19MHz) PARAMETER SYMBOL TEST CONDITION High Level Input Voltage VIH1 VIH2 VIH3 Port 0,1 (Schmitt Input) XI, XTI Port 2,3,4,5,6,8, RESETB, TEST Port 0,1 (Schmitt Input) XI, XTI Port 2,3,4,5,6,8, RESETB, TEST Port 0,1,2,3,6 VOH Output Voltage Low Level Output Voltage VOL Port 0,1,2,3,6 Port 4,5 (Open-Drain) Port 0,1,2,3,6 Port 0,1,2,3,6 High Level Input Leakage Current Low Level Input Leakage Current Supply Current IDD1
(1)
LIMIT MIN.
0.8 VDD VDD-0.5
0.7 VDD
UNIT MAX. VDD VDD VDD V
TYP. -
Low Level Input Voltage
VIL1 VIL2 VIL3
0 0 0 4.2 4.6 -
4.5 4.9 0.4 0.1 1.2
0.2 VDD
0.4
V
0.3 VDD
High Level
(IOH = - 5mA) (IOH = - 100uA) (IOL = 10mA) (IOL = 10mA) (IOL = 1mA)
2 0.6 0.3 3
V
V
Port 0,1,2,3,4,5,6,8 IIH VPPOEX, XTI, RESETB XI Port 0,1,2,3,4,5,6,8 IIL VPPOEX, XTI, TEST XI Dynamic VDD = 5V 10% Main Clock (XI) = 4.19MHz Mode Idle Mode
uA 5 -1.2 15 -3 uA -5 -15 10 mA 5
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SD42C/P1008
DC Electrical Characteristic
(VSS = 0, VDD = 5V 10%, TA = 25E, fx = 4.19MHz)
PARAMETER
SYMBOL
TEST CONDITION MIN. VDD = 3V 10%
LIMIT TYP. MAX. 2
UNIT
Supply Current
IDD2
(1)
Dynamic
Main Clock (XI)
Mode Idle Mode
= 2MHz
-
-
1
mA
IDD3
(2)
Dynamic
Sub Clock (XTI)
VDD = 3V 10%
-
1.5
Mode Idle Mode
IDD4
(2)
= 32.768KHz
-
-
15
IDD5
Main Clock (XI)
Stop Mode
VDD = 5V 10%
-
5
uA
= 4.19MHz
-
-
3
Pull-up Resistor Pull-down Resistor
RL1
VI = 0V, VDD = 5V 10% RESETB
20
-
60 Kohm
RL2
VI = 0V, VDD = 5V 10% TEST
10
-
30
NOTES ) : (1) Data Include power consumption for subsystem clock oscillation. (2) Main system clock oscillation stops and the subsystem clock is used.
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SD42C/P1008
AC Electrical Characteristics
(TA = -40 o +85E, VDD = 2.7 to 6.0V) PARAMETER Cycle Time SYMBOL TEST CONDITION VDD = 4.5 to 6.0V VDD = 2.7 to 3.3V MIN. 0.95 TYP. MAX. 64 UNIT uS
tCY
Main system clock
3.8
-
64
uS
Sub system clock TI0 Input Frequency
114 0 0 0.48 1.8 (1) 10 10 Input 800 1600 3200 3800 400
122 -
125 1 275 300 250 1000 1000 -
uS MHz KHz uS uS uS uS uS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS uS
fTI tTIH tTIL tINTH tINTL tKCY
VDD = 4.5 to 6.0V VDD = 2.7 to 3.3V
TI0 Input High, Low Level Width Interrupt Input High, Low Level Width
VDD = 4.5 to 6.0V VDD = 2.7 to 3.3V INT0 INT1, 2, 3 KS0 to KS7 VDD = 4.5 to 6.0V
SCK Cycle Time
Output Input Output Input
VDD = 2.7 to 3.3V SCK High, Low Level Width
tKH tKL
VDD = 4.5 to 6.0V
Output Input Output Input Output
tKCY /2~50
1600
VDD = 2.7 to 3.3V
tKCY /2~150
100 150 400 400 10
SI Set up Time to SCK High SI Hold Time to SCK High SCK to S0 Output Delay Time
tSIK tKSI tKSO
VDD = 4.5 to 6.0V
Input Output Input Output VDD = 2.7 to 3.3V Input Output
RESETB Low Level
tRSL
(1) 2tcy or 128/fX, depending on the setting of the interrupt mode register.
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SD42C/P1008
AC Timing Measurement Points (Except XI and XTI)
0.8VDD 0.2VDD
Measurement Points
0.8VDD 0.2VDD
Clock Timing tXL XI
1/XI tXH VDD-0.5V 0.4V 1/XTI
XTI
tXTL
tXTH VDD-0.5V 0.4V
Timer Event Counter Timing TI0 tTIL
1/fTI tTIH 0.8VDD 0.2VDD
Serial Transfer Timing tKCY tKL SCK tKH 0.8VDD 0.2VDD tSIK SI tKSO SO Output Data tKSI 0.8VDD 0.2VDD
Input Data
Interrupt Input Timing tINTL INT0~INT3 KS0~KS7 tINTH 0.8VDD 0.2VDD RESETB Input Timing RESETB tRSL 0.2VDD
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SD42C/P1008
RAM Data Retention Characteristics ( in STOP Mode )
(T A = -40 to +85E)
PARAMETER Data Retention Supply Voltage Data Retention Supply Current Release Signal Set Time Oscillation Stabilization Wait Time SYMBOL VDDDR TEST CONDITION MIN. 2.0 TYP. MAX. 6.0 UNIT V
IDDDR
VDDDR = 2.0V
-
0.1
10
uA
tSREL When released by RESETB When released by interrupt Signal
0 -
2 /fx
NOTE 1)
17
-
uS mS mS
tWAIT
NOTE 1) Depends on the setting of the basic interval timer mode register. (refer to the table below) ( fx = 4.19MHz )
BMOD2 0 0 1 1
BMOD1 0 1 0 0
BMOD0 0 1 0 1
Oscillation Stabilization 220/fX (Approximately 250ms) 217/fX (Approximately 31.3ms) 215/fX (Approximately 7.82ms) 213/fX (Approximately 1.95ms)
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SD42C/P1008
RAM Data Retention Timing
When STOP mode is released by RESETB input
Internal Reset Operation Stabilization Wait Time STOP Mode RAM Data retention V DD VDDDR STOP instruction execution tSREL RESETB Operation Mode
tWAIT
When STOP mode is released by interrupt signal
Stabilization Wait Time STOP Mode RAM Data retention VDD VDDDR STOP instruction execution tSREL Operation Mode
Interrupt Signal (Rising Edge)
tWAIT
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SD42C/P1008
SD42P1008
Description
The SD42P1008 is a system evaluation LSI having general EPROM programmer with an adapter socket. The function of this device is exactly same as the SD42C1008 with programming of the internal EPROM. The SD42P1008 is the OTP version of the SD42C1008 with replacement of MASK ROM to EPROM as an internal ROM. a built in One-Time Programming circuit. A programming and verification for the internal EPROM is achieved by using a
Ordering Information
Type NO. SD42P1008 Marking SD42P1008 Package Code QFP-80
Pin Configuration
SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 RESETB P53/EPA7/kS7 P52/EPA6/kS6 P51/EPA5/kS5 80797877767574737271706968676665 SD42P1008 BIAS VLC0 VLC1 VLC2 P60 P61 P62 P63/TEST V SS P80 P81 P82 P83/EPD4 P20/CLO P21 P22
KSI-W029-000
SEG12 1 SEG13 2 SEG14 3 SEG15 4 SEG16 5 SEG17 6 SEG18 7 SEG19 8 SEG20 9 SEG21 10 SEG22 11 SEG23 12 SEG24 13 SEG25 14 SEG26 15 SEG27 16 SEG28 17 SEG29 18 SEG30 19 SEG31 20 COM0 21 COM1 22 COM2 23 COM3 24
25262728293031323334353637383940
64 P50/EPA4/kS4 63 P43/EPA3/kS3 62 P42/EPA2/kS2 61 P41/EPA1/kS1 60 P40/EPA0/kS0 59 XO 58 XI 57 V /OEX PP 56 XTO 55 XTI 54 V D D 53 P33/EPD3 52 P32/EPD2 51 P31/EPD1 50 P30/EPD0 49 P13/EPA11/BUZ 48 P12/EPA10/SO 47 P11/EPA9/SI 46 P10/EPA8/SCK 45 P03/INT3 44 P02/CEX/INT2 43 P01/EPA13/INT1 42 P00/EPA12/INT0/T 41 P23
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SD42C/P1008
Device Operation
The operational modes of the SD42P1008 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for VPP / OEX.
V PP = 12.50.5V
.
PINS MODE READ PROGRAM VERIFY PROGRAM INHIBIT CEX VIL VIL VIL V IH V PP / OEX VIL VPP VIL V PP V DD 5.0V 6.0V 6.0V 6.0V OUTPUT DOUT DIN DOUT High Z
TABLE 1. Operating Modes
MODE PIN NAME EPROM MODE TEST RESETB V IL V IL USER MODE V IH V IH V IL
TABLE 2. The modes of SD42P1008
DC Programming Characteristics
PARAMETER Input Low Voltage Input High Voltage
Output Low Voltage during Verify Output High Voltage during Verify
LIMIT
SYMBOL TEST CONDITION
UNIT MAX. 0.8 VDD 0.45 13.0 6.5 V V V V V V
MIN. VIL VIH VOL VOH VPP VDD IOL = 2.1mA IOH = -400uA -0.1 2.0 2.4 12.5 6.0
Quick-pulse Programming Quick-pulse Programming
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SD42C/P1008
Package Dimension
[ UNIT : Millimeter ]
80 QFP
20.00.1
3.00MAX
14.00.1
17.90.25
0.80
0.350.05
0.150.05
23.90.25 1.80.2
0.80.15
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